Non-volatile memory cell arrays are typically designed to undergo 100K programming and erasure cycles and to retain the stored data in each cell for a significant period of time, such as ten years. The ability of the cell to endure the required number of program and erasure cycles and to retain the data over time strongly depends on the erase operation.
The erase process is schematically illustrated in FIG. 1, to which reference is now made. Prior to erasure, the programmed cells may have a distribution, labeled 10, of threshold voltages above a program verify (PV) level. During erasure, the entire array is erased at once, one pulse at a time. After the first pulse, program distribution 10 has shifted lower, to a distribution 12. After each pulse, the array is “verified” to determine if all the cells have been erased below an erase verify (EV) level. The process is repeated until all of the cells are verified. In FIG. 1, the array required 3 pulses, generating distributions 12, 14 and 16, until all cells had threshold voltages below the EV level. The final distribution 16 is also known as the “erase distribution” 16.
Unfortunately, some of the cells are erased quickly (within 2 pulses in FIG. 1) while others take much longer to erase (the full 3 pulses), resulting in a wide distribution, indicated by arrow 18. Those that have undergone extra erase pulses may be over-erased, a non-ideal state.
Over-erasure may have many causes, among them the non-uniformity in the dimensions of cells within the array, the width of the program distribution of the array cells, the erase algorithm, the electrical as well as the physical characteristics of the cells, etc.
Over-erasure may impact product reliability as well as product performance. One aspect of this is “margin loss”, shown in FIG. 2, to which reference is now made.
An array may begin with program distribution 10, above program verify level PV, and erase distribution 16, below erase verify level EV. A read level RD is defined between the two verify levels. If the cell has a threshold voltage above read level RD, the cell is defined as programmed. Otherwise, the cell is defined as erased
Margins M may be defined as well, in which case, the cell is considered programmed only if its threshold voltage is above a level RD+M0 and erased only if its threshold voltage is below a level RD−M1.
Over time, both distributions may shift lower and spread out, to become distributions 10′ and 16′, respectively. Unfortunately, distributions 10 and 16 may shift enough that a net margin NM, defined as the difference between the highest erase level E1 and the lowest program level P1, no longer guarantees a correct read operation. This is discussed in more detail in Applicant's copending application, U.S. Ser. No. 11/007,332, filed Dec. 9, 2004 which application is incorporated herein by reference.
FIG. 3, to which reference is now made, illustrates the change in net margin NM for a typical array over time after 100K cycles at elevated temperature (150° C.). The example of FIG. 3 is an emulation of a product lifetime, as is known in the art. Net margin NM may reduce from 1200 mV to 300 mV, a change of 900 mV. The smaller net margin NM at 100 min may be insufficient for a read operation.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements